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<h1><center>FPGA Design Elements</center></h1>

<p><center><b>Charles Eric LaForest, PhD.</b>
<br><a href="https://fpgacpu.ca/gateforge/index.html">GateForge Consulting, Ltd.</a></center></p>

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<p class="bordered"><em>This is a continually evolving document. Please email any
feedback to <a href="mailto:eric@fpgacpu.ca?subject=FPGA%20Design%20Elements">eric@fpgacpu.ca</a> or Twitter <a
href="https://twitter.com/elaforest">@elaforest</a> or join the <a href="https://discordapp.com/invite/bWBdwVD">Discord server</a>.</em></p>
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<h2>Introduction</h2>

<ul>
<li> <a href="./outline.html">Outline</a>
<li> <a href="./legal.html">Licence and Disclaimer</a>
</ul>

<h2>References</h2>

<ul>
<li> <a href="./verilog.html">Verilog Coding Standard</a>
<li> <a href="./system.html">System Design Standard</a>
<li> <a href="./handshake.html">Rules for Ready/Valid Handshakes and Synchronization</a>
<li> <a href="./links.html">Useful Links</a>
<li> <a href="./reading.html">References and Reading List</a>
</ul>

<a name="tools"></a>

<h2>Tools</h2>

<ul>

<li><a href="./v2h.py">v2h.py</a>, which converts commented Verilog files into
HTML files. Line comments (no block comments!) are processed as Markdown.
Thus, the web page doesn't get stale as the code evolves. You will need the <a
href="./style.css">CSS Style</a> file to render everything the same, but it's
in the repository and quite simple.

<li><a href="./verilinter">verilinter</a>, which is a small script using <a
href="https://www.veripool.org/wiki/verilator">Verilator</a> and <a
href="https://iverilog.icarus.com/">Icarus Verilog</a> to lint Verilog-2001
files. This little tool catches a lot of simple and not so simple Verilog
mistakes and corner cases.

<li><a href="./generate_file_skeleton.py">generate_file_skeleton.py</a>, which
outputs a skeleton Verilog file in the style used in this book. Takes no
arguments. Simply pipe the output to a new file or your text editor window.

<li><a href="./generate_instance.py">generate_instance.py</a>, which generates
a quick-and-dirty module instance when given a filename containing a module
definition as a parameter. When code is highly modular, writing module
instances takes a large fraction of your writing time. This automates most of
the grunt work. Pipe the output to your text editor window. <b>This is a quick
hack made to work only with the modules in this book.</b>

<li><a href="./generate_fusesoc_core_file">generate_fusesoc_core_file</a>,
which generates a <a href="./FPGA_Design_Elements.core">local core file</a> for
<a href="https://github.com/olofk/fusesoc">FuseSoC</a>, the award-winning
package manager and set of build tools for HDL code. This allows you to
integrate the FPGA Design Elements into your FuseSoC projects.

<li><a href="https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/download.html">Intel Quartus Prime</a>.
The CAD tool suite for Intel (ex-Altera) FPGAs. It's smaller and easier to run
than Xilinx Vivado, and produces excellent RTL-level and post-synthesis
diagrams, which are very useful for checking and debugging designs.

</ul>

<h2>Useful Functions</h2>

<ul>
<li> <a href="./abs_function.html">Absolute Value function</a>
<li> <a href="./max_function.html">Max function</a>
<li> <a href="./min_function.html">Min function</a>
<li> <a href="./gcd_function.html">Greatest Common Divisor function</a>
<li> <a href="./lcm_function.html">Least Common Multiple function</a>
<li> <a href="./clog2_function.html">Ceiling of log<sub>2</sub>(N) function</a>
<li> <a href="./word_count_function.html">Word Count function</a>
<li> <a href="./word_pad_function.html">Word Pad function</a>
<li> <a href="./adjust_to_multiple_function.html">Adjust to Multiple function</a>
</ul>

<h2>Simulation and Test Bench</h2>

<ul>
<li> <a href="./Synthesis_Harness_Input.html">Synthesis Harness Input</a>
<li> <a href="./Synthesis_Harness_Output.html">Synthesis Harness Output</a>
<li> <a href="./Simulation_Clock.html">Simulation Clock</a>
</ul>

<h2>Boolean Logic</h2>

<ul>
<li> <a href="./Constant.html">Constant</a>
<li> <a href="./Bit_Reducer.html">Bit Reducer</a>
<li> <a href="./Annuller.html">Annuller</a>
<li> <a href="./Word_Reverser.html">Word Reverser</a>
<li> <a href="./Word_Reducer.html">Word Reducer</a>
<li> <a href="./Bit_Shifter.html">Bit Shifter</a>
<li> <a href="./Bit_Shifter_Pipelined.html">Bit Shifter (Pipelined)</a>
<li> <a href="./Number_of_Trailing_Zeros.html">Number of Trailing Zeros (ntz)</a>
<li> <a href="./Number_of_Leading_Zeros.html">Number of Leading Zeros (nlz)</a>
<li> <a href="./Population_Count.html">Population Count</a>
<li> <a href="./Hamming_Distance.html">Hamming Distance</a>
<li> <a href="./Bit_Voting.html">Bit Voting</a>
<li> <a href="./Multiplexer_Binary_Behavioural.html">Multiplexer (Binary, Behavioural)</a>
<li> <a href="./Multiplexer_Binary_Structural.html">Multiplexer (Binary, Structural)</a>
<li> <a href="./Multiplexer_One_Hot.html">Multiplexer (One-Hot)</a>
<li> <a href="./Multiplexer_Bitwise_2to1.html">Multiplexer (Bitwise, 2:1)</a>
<li> <a href="./Demultiplexer_Binary.html">Demultiplexer (Binary)</a>
<li> <a href="./Demultiplexer_One_Hot.html">Demultiplexer (One-Hot)</a>
<li> <a href="./Address_Decoder_Static.html">Address Decoder (Static)</a>
<li> <a href="./Address_Decoder_Behavioural.html">Address Decoder (Behavioural)</a>
<li> <a href="./Address_Decoder_Arithmetic.html">Address Decoder (Arithmetic)</a>
<li> <a href="./Address_Translator_Static.html">Address Translator (Static)</a>
<li> <a href="./Address_Translator_Arithmetic.html">Address Translator (Arithmetic)</a>
<li> Extended Boolean operations 
    <ul>
    <li> <a href="./Bitmask_0_Bit_at_Rightmost_1_Bit.html">Bitmask 0 Bit at Rightmost 1 Bit</a>
    <li> <a href="./Bitmask_1_Bit_at_Rightmost_0_Bit.html">Bitmask 1 Bit at Rightmost 0 Bit</a>
    <li> <a href="./Bitmask_Isolate_Rightmost_1_Bit.html">Bitmask Isolate Rightmost 1 Bit</a>
    <li> <a href="./Bitmask_Next_with_Constant_Popcount_pop.html">Bitmask Next with Constant Popcount (via Population Count)</a>
    <li> <a href="./Bitmask_Next_with_Constant_Popcount_ntz.html">Bitmask Next with Constant Popcount (via Number of Trailing Zeros)</a>
    <li> <a href="./Bitmask_Thermometer_from_Count.html">Bitmask Thermometer from Count</a>
    <li> <a href="./Bitmask_Thermometer_to_Rightmost_0_Bit.html">Bitmask Thermometer to Rightmost 0 Bit</a>
    <li> <a href="./Bitmask_Thermometer_to_Rightmost_1_Bit.html">Bitmask Thermometer to Rightmost 1 Bit</a>
    <li> <a href="./Bitmask_Turn_Off_Trailing_1_Bits.html">Bitmask Turn Off Trailing 1 Bits</a>
    <li> <a href="./Bitmask_Turn_On_Trailing_0_Bits.html">Bitmask Turn On Trailing 0 Bits</a>
    <li> <a href="./Turn_Off_Rightmost_1_Bit.html">Turn Off Rightmost 1 Bit</a>
    <li> <a href="./Turn_Off_Rightmost_Contiguous_1_Bits.html">Turn Off Rightmost Contiguous 1 Bits</a>
    <li> <a href="./Turn_Off_Trailing_1_Bits.html">Turn Off Trailing 1 Bits</a>
    <li> <a href="./Turn_On_Rightmost_0_Bit.html">Turn On Rightmost 0 Bit</a>
    <li> <a href="./Turn_On_Trailing_0_Bits.html">Turn On Trailing 0 Bits</a>
    </ul>
<li> <a href="./Dyadic_Boolean_Operator.html">Dyadic Boolean Operator</a>
    <ul>
    <li> <a href="./Dyadic_Boolean_Operations.html">Dyadic Boolean Operations</a>
    </ul>
<li> <a href="./Triadic_Boolean_Operator.html">Triadic Boolean Operator (Dual Output)</a>
</ul>

<h2>Synchronous Logic</h2>

<ul>
<li> <a href="./Clock_Switchover.html">Clock Switchover</a>
<li> <a href="./Register.html">Register</a>
<li> <a href="./Register_Toggle.html">Register (with toggle input)</a>
<li> <a href="./Register_areset.html">Register (with asynchronous reset)</a>
<li> <a href="./Register_Pipeline.html">Register Pipeline</a>
<li> <a href="./Register_Pipeline_Simple.html">Simple Register Pipeline</a>
<li> <a href="./Register_Pipeline_Variable.html">Variable Register Pipeline</a>
<li> Memory
    <ul>
    <li> <a href="./RAM_Single_Port.html">Single-Port RAM (one read/write port)</a>
    <li> <a href="./RAM_Simple_Dual_Port.html">Simple Dual-Port RAM (one read port, one write port)</a>
    <li> <a href="./RAM_Simple_Dual_Port_Dual_Clock.html">Simple Dual-Port RAM (one read port, one write port), with separate read/write clocks</a>
    <li> <a href="./RAM_True_Dual_Port.html">True Dual-Port RAM (two read/write ports)</a>
    <li> <a href="./RAM_generate_empty_init_file.py">Empty Memory Initialization File Generator</a>
    <li> <a href="./RAM_Multiported_LE.html">Multi-Ported Memory using Logic Elements, with Conflict Handling</a>
    <li> <a href="./RAM_1WnR_Replicated.html">Multi-Ported Memory using Replication (1WnR)</a>
    <li> Multi-Ported Memory (LVT)
    <li> Multi-Ported Memory (XOR)
    <li> Multi-Ported Memory (I-LVT)
    <li> CAM
    </ul>
<li> <a href="./Serial_Parallel.html">Serial to Parallel Converter</a>
<li> <a href="./Parallel_Serial.html">Parallel to Serial Converter</a>
<li> <a href="./Duty_Cycle_Generator.html">Duty Cycle Generator</a>
<li> <a href="./Word_Change_Detector.html">Word Change Detector</a>
<li> <a href="./Watchdog_Timer.html">Watchdog Timer</a>
<li> Bressenham Rate Converter
<li> Time Delay (cycles)
<li> Time Delay (fractions of seconds)
<li> Wall Clock
<li> Frequency Counter
</ul>

<h2>Integer Arithmetic</h2>

<ul>
<li> <a href="./Width_Adjuster.html">Width Adjuster</a>
<li> <a href="./Adder_Subtractor_Binary.html">Adder/Subtractor (Binary)</a>
<li> <a href="./Adder_Subtractor_Binary_Multiprecision.html">Multiprecision Adder/Subtractor (Binary)</a>
<li> <a href="./Adder_Subtractor_Binary_Saturating.html">Saturating Adder/Subtractor (Binary)</a>
<li> <a href="./Adder_Subtractor_Binary_Multiprecision_Saturating.html">Multiprecision Saturating Adder/Subtractor (Binary)</a>
<li> Adder/Subtractor (BCD)
<li> <a href="./CarryIn_Binary.html">Carry-In (Binary)</a>
<li> <a href="./Arithmetic_Predicates_Binary.html">Arithmetic Predicates (Binary)</a>
<li> <a href="./Arithmetic_Predicates_Binary_Multiprecision.html">Multiprecision Arithmetic Predicates (Binary)</a>
<li> Up/Down Counters
    <ul>
    <li><a href="./Counter_Binary.html">Binary</a>
    <li>BCD
    <li>Grey
    <li>One-Hot
    <li>Johnson
    </ul>
<li> Number Encoding Converters
    <ul>
    <li> <a href="./Binary_to_One_Hot.html">Binary to One-Hot</a>
    <li> One-Hot to Binary
    <li> <a href="./Binary_to_Gray_Reflected.html">Binary to Gray (Reflected)</a>
    <li> <a href="./Gray_to_Binary_Reflected.html">Gray to Binary (Reflected)</a>
    <li> Binary to Johnson
    <li> Johnson to Binary
    <li> General Shift-Add Converter (e.g. Binary to multi-digit BCD, or to H/M/S)
    </ul>
<li> <a href="./Logarithm_of_Powers_of_Two.html">Logarithm of Powers of Two</a>
<li> Floor of Logarithm Base 2
<li> Ceiling of Logarithm Base 2
<li> Floor of Logarithm Base 10
<li> <a href="./Multiplier_Binary_Parallel.html">Multiplier (Binary, parallel)</a>
<li> Multiplier (BCD, parallel)
<li> Multiplier (Binary, iterative)
<li> Multiplier (BCD, iterative)
<li> <a href="./Divider_Integer_Signed_by_Powers_of_Two_Multiprecision.html">Multiprecision Divider (Powers of Two)</a>
<li> <a href="./Divider_Integer_Signed_by_Powers_of_Two.html">Divider (Powers of Two)</a>
<li> <a href="./Divider_Integer_Signed.html">Signed Integer Divider (Binary, iterative)</a>
    <ul>
    <li> <a href="./Remainder_Integer_Signed.html">Signed Integer Remainder (Binary, iterative)</a>
    <li> <a href="./Quotient_Integer_Signed.html">Signed Integer Quotient (Binary, iterative)</a>
    </ul>
<li> Divider (BCD, iterative)
<li> Comparator
<li> Scaler
<li> <a href="./Accumulator_Binary.html">Accumulator (Binary)</a>
<li> <a href="./Accumulator_Binary_Saturating.html">Saturating Accumulator (Binary)</a>
<li> <a href="./Accumulator_Binary_Multiprecision_Saturating.html">Multiprecision Saturating Accumulator (Binary)</a>
<li> Accumulator (Min)
<li> Accumulator (Max)
<li> Accumulator (Mean)
<li> Accumulator (Weighted Mean)
<li> <a href="./Averager_Powers_of_Two.html">Averager (Powers of Two)</a>
<li> Zero-Crossing Detector
<li> Pseudo-Random Number Generators (PRNGs)
    <ul>
    <li>Linear Feedback (Fibonacci) (self-synchronizing?)
    <li>PCG family
    </ul>
<li> Linear interpolation from table (2^n size)
</ul>

<h2>Pulse Logic</h2>

<ul>
<li> <a href="./Pulse_Latch.html">Pulse Latch</a>
<li> <a href="./Pulse_Generator.html">Pulse Generator</a>
<li> <a href="./Pipeline_to_Pulse.html">Pipeline to Pulse Interface</a>
<li> <a href="./Pulse_to_Pipeline.html">Pulse to Pipeline Interface</a>
<li> <a href="./Pulse_Divider.html">Pulse Divider</a>
</ul>

<h2>Elastic Pipelines</h2>

<ul>
<li> <a href="./Pipeline_Skid_Buffer.html">Pipeline Skid Buffer</a>
<li> <a href="./Pipeline_Half_Buffer.html">Pipeline Half-Buffer</a>
<li> <a href="./Pipeline_FIFO_Buffer.html">Pipeline FIFO Buffer</a>
<li> <a href="./Skid_Buffer_Pipeline.html">Skid Buffer Pipeline</a>
<li> <a href="./Pipeline_Credit_Buffer.html">Pipeline Credit Buffer</a>
<li> <a href="./Pipeline_Credit_Gate.html">Pipeline Credit Gate</a>
<li> <a href="./Pipeline_Fork_Lazy.html">Pipeline Fork (Lazy)</a>
<li> <a href="./Pipeline_Fork_Eager.html">Pipeline Fork (Eager)</a>
<li> <a href="./Pipeline_Fork_Blocking.html">Pipeline Fork (Blocking)</a>
<li> <a href="./Pipeline_Synchronizer_Lazy.html">Pipeline Synchronizer (Lazy)</a>
<li> <a href="./Pipeline_Join.html">Pipeline Join</a>
<li> <a href="./Pipeline_Join_Lazy.html">Pipeline Join (Lazy)</a>
<li> <a href="./Pipeline_Branch_One_Hot.html">Pipeline Branch (One-Hot)</a>
<li> <a href="./Pipeline_Merge_One_Hot_Lazy.html">Pipeline Merge (One-Hot, Lazy)</a>
<li> <a href="./Pipeline_Merge_One_Hot.html">Pipeline Merge (One-Hot)</a>
<li> <a href="./Pipeline_Merge_Priority.html">Pipeline Merge (Priority)</a>
<li> <a href="./Pipeline_Merge_Round_Robin.html">Pipeline Merge (Round-Robin)</a>
<li> <a href="./Pipeline_Sink.html">Pipeline Sink</a>
<li> <a href="./Pipeline_Gate.html">Pipeline Gate</a>
<li> <a href="./Pipeline_Credit_Gate.html">Pipeline Credit Gate</a>
<li> <a href="./Pipeline_Stall_Smoother.html">Pipeline Stall Smoother</a>
<li> <a href="./Pipeline_Iterator.html">Pipeline Iterator</a>
<li> <a href="./Pipeline_Handshake_Multiplier.html">Pipeline Handshake Multiplier</a>
<li> <a href="./Pipeline_Serial_Parallel.html">Pipeline Serial to Parallel Converter</a>
</ul>

<h2>Arbitration and Synchronization</h2>

<ul>
<li> <a href="./Priority_Encoder.html">Priority Encoder</a>
<li> <a href="./Arbiter_Priority.html">Priority Arbiter</a>
<li> <a href="./Arbiter_Round_Robin.html">Round-Robin Arbiter</a>
<!-- <li> Matrix Arbiter -->
<li> <a href="./Synchronous_Muller_C_Element.html">Synchronous Muller C-Element</a>
</ul>

<a name="cdc"></a>
<h2>Clock Domain Crossing (CDC)</h2>

<ul>
<li> <a href="./cdc.html">A Primer on CDC Theory</a>
<li> <a href="./CDC_Bit_Synchronizer.html">CDC Bit Synchronizer</a>
<li> <a href="./CDC_Word_Synchronizer.html">CDC Word Synchronizer</a>
<li> <a href="./CDC_Pulse_Synchronizer_4phase.html">CDC Pulse Synchronizer (4-phase)</a>
<li> <a href="./CDC_Pulse_Synchronizer_2phase.html">CDC Pulse Synchronizer (2-phase)</a>
<li> <a href="./Weinstein_Flancter.html">Weinstein Flancter</a>
<li> <a href="./CDC_Flag_Bit.html">CDC Flag Bit</a>
<li> <a href="./Reset_Synchronizer.html">Reset Synchronizer</a>
<li> <a href="./CDC_FIFO_Buffer.html">CDC FIFO Buffer</a>
<li> <a href="./CDC_FIFO_Repacker.html">CDC FIFO Repacker</a>
</ul>


<h2>Interfaces</h2>

<ul>
<li> <a href="./IDELAYCTRL_Instance.html">IDELAYCTRL Instance</a>
<li> <a href="./Deserializer_Differential_1toN.html">Differential Data Deserializer, 1 to N Ratio</a>
<li> <a href="./Register_IO_Single_Ended.html">I/O Register (Single-Ended)</a>
<li> <a href="./Debouncer_Low_Latency.html">Debouncer (Low Latency)</a>
<li> <a href="./Quadrature_Decoder.html">Quadrature Decoder</a>
<li> Seven-segment Display Decoder (single BCD digit)
<li> Key Encoder (NxM, no rollover)
<li> Stepper Motor Driver
<li> Servo Motor Driver
<li> Basic I2C (just enough to read/write one address upon a trigger)
<li> Basic UART (no flow-control, no FIFO, fixed rate via parameter, enough to receive simple commands, or dump data)
<li> Basic NeoPixel Driver (really another kind of UART)
</ul>

<h2>Analog Signal Handling</h2>

<ul>
<li> Basic waveform generator (table-driven)
<li> PWM driver (for sound, motor, LEDs)
<li> Sound sample player (simple DAC data, played as PWM?)
<li> Basic DAC (PMW and output to resistor ladder)
<li> Basic ADC (SAR using PWM DAC and LVDS input)
<li> Sound sample recorder (ADC + Memory)
</ul>

<h2>Hashing and Pattern Matching</h2>

<ul>
<li>Simple substring match
<li>Hash Functions (misc. TBD)
<li>Bloom or Cuckoo Filter
</ul>

<h2>Communications</h2>

<ul>
<li> Clock encoding and recovery (e.g. NRZ, MFM, DM, etc... as in old magnetic storage)
<li> Basic LVDS/TMDS communication (like UART, building block for LCD control, HDMI, multi-FPGA design, serial wire mux)
<li> Pseudo-differential communication (slower, using regular pins)
<li> Single-wire communication (tri-state bidir pin, self-clocked like NeoPixel)
<li> Hamming Code Generator
<li> Hamming Code Checker (EDAC)
<li> CRC Generator
<li> CRC Checker
<li> 8b/10b Encoder
<li> 8b/10b Decoder
</ul>

<h2>Miscellaneous Bits</h2>

<ul>
<li> <a href="./fsm.html">On The Implementation of Finite State Machines</a>
<li> <a href="./open.html">Open Design Questions</a>
<li> <a href="./debian.html">Using <s>Altera's</s> Intel's USB-Blaster on Debian Linux</a>
</ul>

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